CT8022 is what has been developed in DSPG Company can realize the algorithmic specialized DSP chip of many kinds of compression. It can accept the intersection of 8bit A/ μ and data or the intersection of 16bit and linear data, the whole concurrent implementation of 64/ 128kbits/ s that external serial A/ D offer / compress and decompress while being half duplex, form which the host computer determines through the command word on the grounds of compressing it. It is 8 to compress. 5/ 6. 3/ 5. 3/ 4. 8/ 4. Data of 1kbits/ s. It is 6 to act as and compress. 3/ 5. 3kbits/ s hour, accords with ITU-G. 723. A standard. There are real-time echo offsetting and automatic gain control circuits in CT8022. It is at sending end and sample receiving end at the time of clock out-of-step,system can automatic adding or last frame. In addition, CT8022 offers DTMF signal and calls out and continue production and detection function of the sound. Can apply to H. 323 and H. 324 multimedia videophone / systems such as the video conference,etc., it also can be used for realizing the digital data / pronunciation are with spreading (DSVD) Technology.

A pin description

CT8022 has 128 base pins, are divided into 6 kinds.

( 1) Main machine interface pin

HSTDB0- 7: Data bus of the host computer.

HSTAB0- 3: Host computer address line. HSTAB0 used for choose 16 high 8 or low 8 of bit control word act as for choose low 8 0 hour among them, choose 8 high at 1 o’clock.

HSTRDN: The host computer reads the enabling signal. Allow the read data in the selected main machine interface register after from HSTAB1- 3 decipher of the host computer.

HSTWRN: The host computer writes the enabling signal. Allow the read-in data in the selected main machine interface register from HSTAB1- 3 decipher of the host computer.

HSTCSN: Main machine interface choose signals. While reading and writing CT8022, this pin and HSTRDN, HSTWRN and HSTAB0- 3 act on together. When HSTCSN is effective, HSTAB0- 3 should maitain unchanged. In DMA way, this signal should be put for being invalid.

( 2) Data / programm store pin

MDB0- 15: Outside data storage data bus. ADDR0- 15: Outside data memory address bus. BSEL: The external data bus byte is chosen. This pin is useful when connecting not 16 memory of width. DRDN: The external data storage is read and allowed. DWRN: The data memory write of outside is allowed. PRDN: The procedure memory of outside is read and allowed. PRWN: It is allowed that the procedure memory of outside is written. CREADN: Read outside procedure and data storage pin at the same time. DCSN: External data storage chip selection signal. Earth when not needing.

( 3) Pin of the clock

SLK: CODEC interface displacement clock. FSYNC: CODEC interface frame synchronized clock. XIN: Clock input of crystal / outside. XOUT: Ausgang of crystal. CLKOUT: Key frequency of CT8022 speech compression chip. By the internal frequency 45. 056MHz frequency demultiplication got. The frequency demultiplication factor can be set up through ordering. PLLR, PLLC, PLLT, AVCC, AGND: PLL supports the base pin. The connecting means is shown as in Fig. 1. PLLBYPASS: Forbid internal PLL. Used for in XIN end connecting 90 directly. 112MHz clock spends hour.

( 4) CODEC pin

DX0: Used in serial output and already decompress signals to CODEC0. DR0: Used in from CODEC0 Serial Input 8/ 16bit form signal. DX1: Used in serial output and already decompress signals to CODEC1. DR1: Used in from CODEC1 Serial Input 8/ 16bit form signal.

( 5) DMA pin

TXDREQ: DMA sends the request signal. Machine format transmission can adopt DMA way or host computer access mode. The concrete way can be passed to the control register of the hardware (HCR) during initialisation Write the control command is controlled.

TXDACKN: DMA sends and allows.

RXDREQ: DMA receives the request signal. RXDACKN: DMA receives the enabling signal.

( 6) Other pins

GND1- 18: Earth the pin. VCC1- 18: Connect 5V power. IRQN: Break request signal. RSTN: Reset ports. GPIO0- 7: Foot of common I/ O. Compatible with this device serial CT8015 in the past. BRQN, ABORTN, EINTN: Keep the pin. Can pull upward the resistance and link with VCC through 10kΩ. BGRNTN, BRDN: Keep, disconnect. EXTP, BMODE, DBG, BOOT, URST, TEST: Keep, earth.

The ones that should prove are: In the above-mentioned all base pin names, if the last letter is N, show this base pin is low and effective.

2 operating principles

2 . Interface of 1 and CODEC

CT8022 can be with one or two 8 bit A/ μ rate coders (A/ D and D/ A) directly Link up, can link with 16 linear coders too. It if you can’t regard as, input /outcoming signal at,parameters concrete that be can confirm by interface command of the host computer on interfaced. When using two coders, should guarantee its type is the same. CT8022 can provide the clock signal for CODEC, can also use the common external clock signal with the coder. When CT8022 provides the clock signal for CODEC, clock SCLK and FSYNC but frequency demultiplication receive through programming by clock of inside their. The sampling frequency of CODEC is FSYNC. The clock relation within SCLK, FSYNC and CT8022 is:

SCLK =Internal clock / (N + 1) of CT8022 ,Among them 3 is less than or equal to N and less than or equal to 31;

FSYNC =SCLK/ ( M+ 1) ,Among them 18 is less than or equal to M and less than or equal to 1023.

M, N the intersection of frequency demultiplication and factor in the type, concrete value can use, order load during initialisation according to sampling frequency.

2. 2 outside SRAM

CT8022 needs 8k at least