Foreword, with the development of multimedia and network technique, the intersection of digital image and large characteristic of information volume requirement for video condensing technology high, so, the digital information processing technique of the specialized high speed becomes the direction of development. Among them, in the hardware technology, C5000 series DSP that TI introduced has brought the handling capacity of the digital signal processor up to a new height, make the research focal point of the signal processing system get back to the software algorithm again. In compressing algorithm research, a plurality of algorithms such as DCT, wavelet are being favored because of its high reliability and efficiency. Systematic hardware design TMS320C5409 is 100MHz as the feasibility analysis TMS320C5409 clock rate of the host processor, the cost performance is extremely high. Adopt it around bus line of a group of procedures, 3 groups of data buses and improved Harvard structure that is set up of 4 groups of address buses, fetching location and reading can go on at the same time. There are independent hardware multipliers, the ones that help to realize optimizing in algorithms such as convolution, numerical filtering, FFT, matrix arithmetic,etc. repeat the operation of multiplication in a large amount. Circulate special orders such as addressing, location bit-reversed order,etc., these orders make the addressing, preface and calculated speed in operation such as FFT, convolution improve greatly. There are a series of or independent DMA bus of multibank, and the procedure of CPU, data bus concurrent working.

In this system, TMS320C5409, as the host processor, the task is to realize JPEG compressed encoding. Through analyzing that easy to get, it is 640 to look on as and deal with a frame size